The high electron mobility transistor (HEMT) is a type of field effect transistor (FET) having a heterojunction between a channel layer and a barrier layer whose electron affinity is smaller than that of the channel layer. A group III-N HEMT device is one made of elements in column III of the periodic table, such as aluminum (Al), gallium (Ga), and indium (In), and nitrogen (N) in column V of the periodic table. A two-dimensional electron gas (2DEG) forms in the channel layer of a group III-N HEMT device due to a polarization induced charge at the channel-barrier layer interface. The 2DEG has a high electron mobility that facilitates low channel resistance and high-speed switching during device operation.
In typical HEMT devices, the 2DEG arises naturally at the interface of the III-N materials forming the heterojunction, meaning the typical HEMT device will conduct in the absence of a gate potential. In other words, the typical HEMT device is a normally “on” device. A negatively-biased voltage may be applied to the gate electrode to deplete the 2DEG and thereby turn off the device. Accordingly, the typical HEMT device is also referred to as a “depletion-mode” HEMT.
FIG. 1 shows a cross-sectional view of a prior art structure for a depletion-mode HEMT device. The HEMT device 100 shown in FIG. 1 begins with substrate 102. An optional buffer layer 104, also known as a nucleation layer, can be deposited on substrate 102 to provide a surface on which high-quality gallium nitride (GaN) may be grown. Epitaxial growth of gallium nitride (GaN) forms a channel layer 106 on buffer layer 104.
Next, a barrier layer 108, is formed on channel layer 106. Barrier layer 108 comprises a material suitable to form a hetero-junction with the channel layer 106. Electrodes 112 and 114 formed on barrier layer 108 act as the source and drain, respectively, of the HEMT device 100. Source and drain electrodes 112 and 114 may comprise any suitable material that forms an ohmic contact with the barrier layer 108. Gate electrode 110 is also formed on barrier layer 108, between the source electrode 112 and drain electrode 114. Gate electrode 110 comprises a material that forms a non-ohmic contact (a contact which does not exhibit linear I-V characteristics) with the barrier layer 108.
During device operation of the foregoing HEMT device 100, a 2DEG forms on the channel layer side of the interface between channel layer 106 and barrier layer 108, allowing current to flow between the source electrode 112 and the drain electrode 114. A negative voltage (relative to substrate 102) may be applied to gate electrode 110 to deplete the 2DEG and shut off the flow of current between the source electrode 112 and the drain electrode 114, turning off the HEMT device 100.
Group III-N HEMT devices exhibit a number of desirable characteristics, including high breakdown voltage, high current density, high electron velocity, and low on resistance, making them particularly suited for high power and high frequency applications. However, the typical depletion-mode HEMT device's normally on state makes it unsuitable for many applications as the depletion-mode HEMT conducts current before other circuitry is fully powered and operational.
To resolve this issue, a number of different approaches have been explored to create a normally “off”, or enhancement-mode, HEMT device. One conventional approach is to heavily p+ dope a semiconductor gate to form a P-N junction with the underlying barrier layer. However, the P-N junction has a high current leakage resulting in increased power consumption and heat generation, both undesirable transistor characteristics. Another conventional approach is disclosed by Kanamura et al., Enhancement-Mode GaN MIS-HEMTS with n-GaN/i-AlN/n-GaN Triple Cap Layer and High-k Gate Dielectrics, IEEE Electron Device Letters, Vol. 31, No. 3 (March 2010), which is incorporated herein by reference. Kanamura et al. discloses the use of a recessed gate structure to shift the threshold voltage of the HEMT device positive. To form the recessed gate structure of Kanamura et al., the barrier layer must be etched to a precise depth in order to obtain a desired threshold voltage.
Precise etching of the barrier layer was attempted by Kanamura et al., however etching the barrier layer is generally considered unsuitable for large-scale manufacturing where variations occur across a wafer during each processing step, making it difficult to precisely control the etching depth of the barrier layer for each HEMT device formed on the wafer. An HEMT device formed on one corner of the wafer using the method disclosed by Kanamura et al. will have a drastically different threshold voltage compared to another HEMT device formed on the opposite corner of the wafer—making the HEMT device unsuitable for most modern applications which require relatively precise and consistent transistor characteristics to properly function.
There is, therefore, an unmet demand for enhancement-mode HEMT devices having enhanced conductivity and that are suitable for large-scale manufacturing.